1. Field of the Invention
This invention relates to a method for manufacturing a semiconductor device with a multilayer wiring structure, including the improved step of forming an insulating film such as an interlayer insulating film, or a top passivation film, which covers a wiring layer.
2. Description of the Related Art
In accordance with increases in the integration of semiconductor devices, techniques for forming multiple layers of wiring materials on a substrate have been developed. In the techniques, a technique for planarising an interlayer insulating film or a top passivation film has been regarded as important.
The conventional step of forming multilayer wiring will be explained with reference to FIG. 1.
First, an element region and a contact region, which are not shown, are formed in a semiconductor substrate 30, and then a lower insulating film 31 with a thickness of about 1000 nm is formed on the resultant structure by the CVD under normal pressure.
Subsequently, contact holes are formed in the lower insulating film 31 to connect the wiring to the element and contact regions.
A first wiring material (made of aluminum, which contains, for example, 1% Si and 0.5% Cu) for a lower wiring layer is deposited and patterned by photolithography and RIE (Reactive Ion Etching), thereby forming lower wires 32.
The lower wires 32 have a thickness of about 900 nm and are arranged with a pitch of about 600 nm at minimum.
Subsequently, a plasma CVD insulating film 33 with a thickness of about 800 nm is formed on the resultant structure by plasma CVD.
However, where the wires 32 are so thinned in a highly integrated LSI device, the above-described usual plasma CVD cannot sufficiently supply reactive gas or inject ions to fine spaces defined between extremely thin wires. Accordingly, the CVD insulating film 33 cannot sufficiently grow in such spaces.
In particular, those portions of the insulating film 33, which are deposited on the corners of the fine spaces between the thin wires, are very thin and may have overhanging cross sections.
More specifically, as is shown in FIG. 1, a void 34 may be formed between overhanging portions 33a and 33b of the plasma CVD insulating film 33. Further, the overhanging portions of the insulating film 33 may adversely affect deposition of a second wiring material for an upper wiring layer, or patterning of the upper wiring layer, thereby causing a serious defect such as disconnection of upper wires due to defective forming of the upper wiring layer.
These problems indicate that the plasma CVD process as a process for forming an interlayer insulating film has reached its technical limit as the wires have extremely been refined.
In addition, where the thickness of the CVD insulating film 33 is partially thin in the spaces between fine wires, the quality of thin portions of the film 33 is low because of insufficient supply of reactive gas or insufficient ion injection.
Accordingly, if the CVD process is used to form a top passivation film, moisture, alkali ions, etc. may enter the LSI device from the outside through those corners of the spaces between the wires located under the top passivation film, which are not sufficiently insulated by the plasma CVD insulating film, thereby degrading the reliability of the device.
An APL (Advanced Planarisation Layer) process as one of techniques for planarising an interlayer insulating film is disclosed, for example, in a document "Matsuura et al. IEEE Tech. Dig., p 117, 1994", and in a document "Semiconductor International, DECEMBER 1994, pp 85-88".
In the APL process, SiH.sub.4 gas is reacted with H.sub.2 O.sub.2 gas, as an oxidizing agent, at a low temperature of e.g. 0.degree. C. under a vacuum pressure, to thereby form on lower wires a reflow SiO.sub.2 film as an interlayer insulating film.
This process is advantageous in that deposition of an insulating film in the spaces between the lower wires and planarisation of the insulating film can be performed at the same time, and hence in that a multilayer wiring structure can be formed at low cost by virtue of the simultaneous deposition and planarisation.
However, as explained above, the interlayer insulating film obtained by the above-described conventional plasma CVD process cannot sufficiently grow in the spaces defined between lower thin wires, and may have portions of overhanging cross sections. As a result, a void may be formed in the spaces between the wires, and serious defects due to defective forming of the upper wiring layer, such as breakage of upper wires, short-circuiting in the wiring structure, etc., may occur.
Moreover, as explained above, in the top passivation film obtained by the conventional plasma CVD process, moisture, alkali ions, etc. may well enter the device from the outside through those corners of the spaces between the wires located under the top passivation film, which are not sufficiently insulated by the plasma CVD insulating film, thereby degrading the reliability of the device.